/* * This is a synchronous trap on either an x87 instruction (due to an * unmasked error on the previous x87 instruction) or on an SSE/SSE2 etc * instruction due to an error on the instruction itself. * * If trap actually generates a signal, then the fpu state is saved * and then copied onto the process's user-stack, and then recovered * from there when the signal returns (or from the jmp_buf if the * signal handler exits with a longjmp()). * * All this code need to do is save the reason for the trap. * For x87 interrupts the status word bits need clearing to stop the * trap re-occurring. * * The mxcsr bits are 'sticky' and need clearing to not confuse a later trap. * * Since this is a synchronous trap, the fpu registers must still belong * to the correct process (we trap through an interrupt gate so that * interrupts are disabled on entry). * Interrupts (these better include IPIs) are left disabled until we've * finished looking at fpu registers. * * For amd64 the calling code (in amd64_trap.S) has already checked * that we trapped from usermode. */