//Original:/testcases/core/c_comp3op_dr_mix/c_comp3op_dr_mix.dsp // Spec Reference: comp3op dregs mix # mach: bfin .include "testutils.inc" start imm32 r0, 0x01234567; imm32 r1, 0x89abcdef; imm32 r2, 0x56789abc; imm32 r3, 0xdef01234; imm32 r4, 0x23456899; imm32 r5, 0x78912345; imm32 r6, 0x98765432; imm32 r7, 0x12345678; R0 = R0 + R0; R1 = R0 - R1; R2 = R0 & R2; R3 = R0 | R3; R4 = R0 & R4; R5 = R0 & R5; R6 = R0 | R6; R7 = R0 & R7; CHECKREG r0, 0x02468ACE; CHECKREG r1, 0x789ABCDF; CHECKREG r2, 0x02408A8C; CHECKREG r3, 0xDEF69AFE; CHECKREG r4, 0x02440888; CHECKREG r5, 0x00000244; CHECKREG r6, 0x9A76DEFE; CHECKREG r7, 0x02040248; imm32 r0, 0x01231567; imm32 r1, 0x89ab1def; imm32 r2, 0x56781abc; imm32 r3, 0xdef01234; imm32 r4, 0x23451899; imm32 r5, 0x78911345; imm32 r6, 0x98761432; imm32 r7, 0x12341678; R0 = R1 + R0; R1 = R1 - R1; R2 = R1 & R2; R3 = R1 | R3; R4 = R1 & R4; R5 = R1 & R5; R6 = R1 | R6; R7 = R1 & R7; CHECKREG r0, 0x8ACE3356; CHECKREG r1, 0x00000000; CHECKREG r2, 0x00000000; CHECKREG r3, 0xDEF01234; CHECKREG r4, 0x00000000; CHECKREG r5, 0x00000000; CHECKREG r6, 0x98761432; CHECKREG r7, 0x00000000; imm32 r0, 0x01234527; imm32 r1, 0x89abcd2f; imm32 r2, 0x56789a2c; imm32 r3, 0xdef01224; imm32 r4, 0x23456829; imm32 r5, 0x78912325; imm32 r6, 0x98765422; imm32 r7, 0x12345628; R0 = R2 + R0; R1 = R2 - R1; R2 = R2 & R2; R3 = R2 | R3; R4 = R2 & R4; R5 = R2 & R5; R6 = R2 | R6; R7 = R2 & R7; CHECKREG r0, 0x579BDF53; CHECKREG r1, 0xCCCCCCFD; CHECKREG r2, 0x56789A2C; CHECKREG r3, 0xDEF89A2C; CHECKREG r4, 0x02400828; CHECKREG r5, 0x50100224; CHECKREG r6, 0xDE7EDE2E; CHECKREG r7, 0x12301228; imm32 r0, 0x01234563; imm32 r1, 0x89abcde3; imm32 r2, 0x56789ab3; imm32 r3, 0xdef01233; imm32 r4, 0x23456893; imm32 r5, 0x78912343; imm32 r6, 0x98765433; imm32 r7, 0x12345673; R0 = R3 + R0; R1 = R3 - R1; R2 = R3 & R2; R3 = R3 | R3; R4 = R3 & R4; R5 = R3 - R5; R6 = R3 | R6; R7 = R3 & R7; CHECKREG r0, 0xE0135796; CHECKREG r1, 0x55444450; CHECKREG r2, 0x56701233; CHECKREG r3, 0xDEF01233; CHECKREG r4, 0x02400013; CHECKREG r5, 0x665EEEF0; CHECKREG r6, 0xDEF65633; CHECKREG r7, 0x12301233; imm32 r0, 0x41234567; imm32 r1, 0x49abcdef; imm32 r2, 0x46789abc; imm32 r3, 0x4ef01234; imm32 r4, 0x43456899; imm32 r5, 0x48912345; imm32 r6, 0x48765432; imm32 r7, 0x42345678; R0 = R4 + R0; R1 = R4 - R1; R2 = R4 & R2; R3 = R4 | R3; R4 = R4 & R4; R5 = R4 & R5; R6 = R4 | R6; R7 = R4 & R7; CHECKREG r0, 0x8468AE00; CHECKREG r1, 0xF9999AAA; CHECKREG r2, 0x42400898; CHECKREG r3, 0x4FF57ABD; CHECKREG r4, 0x43456899; CHECKREG r5, 0x40012001; CHECKREG r6, 0x4B777CBB; CHECKREG r7, 0x42044018; imm32 r0, 0x05234567; imm32 r1, 0x85abcdef; imm32 r2, 0x55789abc; imm32 r3, 0xd5f01234; imm32 r4, 0x25456899; imm32 r5, 0x75912345; imm32 r6, 0x95765432; imm32 r7, 0x15345678; R0 = R5 + R0; R1 = R5 - R1; R2 = R5 & R2; R3 = R5 | R3; R4 = R5 & R4; R5 = R5 & R5; R6 = R5 | R6; R7 = R5 & R7; CHECKREG r0, 0x7AB468AC; CHECKREG r1, 0xEFE55556; CHECKREG r2, 0x55100204; CHECKREG r3, 0xF5F13375; CHECKREG r4, 0x25012001; CHECKREG r5, 0x75912345; CHECKREG r6, 0xF5F77777; CHECKREG r7, 0x15100240; imm32 r0, 0x01264567; imm32 r1, 0x89a6cdef; imm32 r2, 0x56769abc; imm32 r3, 0xdef61234; imm32 r4, 0x23466899; imm32 r5, 0x78962345; imm32 r6, 0x98765432; imm32 r7, 0x12365678; R0 = R6 + R0; R1 = R6 - R1; R2 = R6 & R2; R3 = R6 | R3; R4 = R6 & R4; R5 = R6 & R5; R6 = R6 | R6; R7 = R6 & R7; CHECKREG r0, 0x999C9999; CHECKREG r1, 0x0ECF8643; CHECKREG r2, 0x10761030; CHECKREG r3, 0xDEF65636; CHECKREG r4, 0x00464010; CHECKREG r5, 0x18160000; CHECKREG r6, 0x98765432; CHECKREG r7, 0x10365430; imm32 r0, 0x01237567; imm32 r1, 0x89ab7def; imm32 r2, 0x56787abc; imm32 r3, 0xdef07234; imm32 r4, 0x23457899; imm32 r5, 0x78917345; imm32 r6, 0x98767432; imm32 r7, 0x12345678; R0 = R7 + R0; R1 = R7 - R1; R2 = R7 & R2; R3 = R7 | R3; R4 = R7 & R4; R5 = R7 - R5; R6 = R7 | R6; R7 = R7 & R7; CHECKREG r0, 0x1357CBDF; CHECKREG r1, 0x8888D889; CHECKREG r2, 0x12305238; CHECKREG r3, 0xDEF4767C; CHECKREG r4, 0x02045018; CHECKREG r5, 0x99A2E333; CHECKREG r6, 0x9A76767A; CHECKREG r7, 0x12345678; imm32 r0, 0x00000001; imm32 r1, 0x00020003; imm32 r2, 0x00040005; imm32 r3, 0x00060007; imm32 r4, 0x00080009; imm32 r5, 0x000a000b; imm32 r6, 0x000c000d; imm32 r7, 0x000e000f; R0 = R1 + R2; R1 = R3 - R2; R2 = R4 & R3; R3 = R5 | R4; R4 = R6 & R7; CHECKREG r0, 0x00060008; CHECKREG r1, 0x00020002; CHECKREG r2, 0x00000001; CHECKREG r3, 0x000A000B; CHECKREG r4, 0x000C000D; CHECKREG r5, 0x000a000b; CHECKREG r6, 0x000c000d; CHECKREG r7, 0x000e000f; pass